*********************************************************
hagiwara-yoshiaki@aiplab.com ( http://www.aiplab.com/ )

hagiwara@ssis.or.jp ( http://www.ssis.or.jp/en/index.html )

*********************************************************
           return to the TOP Page
*********************************************************



*********************************************************

http://www.aiplab.com/index1_List_of_Books_and_Journal_Publication.html

http://www.aiplab.com/index2_Conference_Publication.html

http://www.aiplab.com/index3_International_Contributions_and_Awards.html

http://www.aiplab.com/index4_Important_Japanese_Patents.html

http://www.aiplab.com/index5_My_Work_Summary.html


http://www.aiplab.com/index6_Important_Publication_and_Patent_Works.html

*********************************************************

You are now in

http://www.aiplab.com/index6_Important_Publication_and_Patent_Works.html

*********************************************************



Hagiwara Important Publication & Patent Works

Japanese Patent 1975-127646 on N+NP+NP junction Pinned Photodiode



Japanese Patent 1975-127647 on N+NP+N junction Pinned Phtotodiode



Japanese Patent 1975-124985 on P+NPNsub junction Pinned Photodiode












(1) 1973 Paper

"The Influence of Interface States on Incomplete Charge Transfer
in Overlapping Gate Charge Coupled Devices",
IEEE Journal of Solid State Circuits, Vol. SC 8, No.2, April 1973


(2) 1974 Paper ( Hagiwara PhD student Paper )

"Charge Transfer of Buried Channel Charge Coupled Devices"
Proceeding of International Solid State Circuit Conference (ISSCC),
San Francisco, Februrary 1974.




(3) 1974 Paper

"Final Stage of the Charge Transfer Process in Charge Coupled Devices"
IEEE Transactions on Electrron Devices, VOl. ED-21, No.4, April 1974

(4) 1976 Paper

128-bit Comparator Chip




(5) 1977 Paper

"Two Phase CCD with Narrow Channel Transfer Regions"
Proceeding of the 9th Conference on Solid State Devices, Tokyo 1977;
Japanese Journal of Applied Physics, Vol 17 (1978) Supplement 17-1,pp.255-261

(6) 1978 Paper

"A 380H x 488V CCD Imager with Narrow Channel Transfer Gates"
Proceeding of the 10th Conference on Solid State Devices, Tokyo 1978;
Japanese Journal of Applied Physics, Vol 18 (1979) Supplement 18-1,pp.335-340










(7) 1979

Paper Invited Talk at CCD'79 at Edinburgh, Scotland UK


(8) 1989 Paper

Paper on the Fast Cache 4 Mega bit Cache SRAM at ISSCC1989


(9) 2001 Paper

Invited Talk at ESSCIRC2001


(10) 2008 Paper

Invited Talk at ESSCIRC2008

(11) 2013 Talk

ISSCC2013 Plenary Panel Talk



(12) 2019 Paper

3DIC2019 Conference at Sendai, Japan 2019


(13) EDTM2020 PaperID3C-4

"Simulation and Device Characterization of the P+PN+P Junction Type

Pinned Photodiode and Schottky Barrier Photodiode"





*******
Awards
*******

1978年 ソニー中央研究所 Crystal Award 優秀研究賞(個人)




1988年 ソニーCEO アワード (グループ受賞 ) 

  ( デジカメ用の高速 4M Cache SRAMの開発 )

1996年 ソニー発明考案実施特別表彰一級最優秀賞(個人受賞)

   ( 電子シャッター&ガンマ特性機能 )




2000年 ソニーSCプレジデントアワード(個人受賞 )

  ( SONY 対 Fairchild社の特許戦争への貢献 )

2000年  ソニー発明考案実施褒賞一級(個人受賞)

  ( SONY HAD = Pinned Photodiode + VOD )




2001年 IEEE Fellow

2002年 米国 カリフォルニア工科大学 Distinguished Alumni Award 

2008年 IEEE ICMTS運営委員会 Service Award (功労表彰)

2013年 IEEE ISSCC運営委員会 Service Award (功労表彰)

2018年 IEEE Life Fellow

***********
Publications
***********

(1)「CCDとその応用技術」 筆頭共著 昭和55年11月 トリケップス社

(2)「The Computer Engineering Handbook 」 共著 平成15 年12月 CRC Press

(3)「人工知能を支えるデジタル回路の世界」単著 平成29年3月 青山社

(4) 「The Influence of Interface States on Incomplete Charge Transfer
  in Overlapping Gate Charge-Coupled Devices」 共著 
  IEEE Journal of Solid State Circuits, Volume SC-8, No.2
  pp.125-138, April 1973

(5) 「Charge Transfer in Buried-Channel Charge Coupled Devices」筆頭共著
  IEEE/ISSCC1974 Digest of Technical Papers, Philadelphia, PA,
  pp.146-147, February 1974

(6) 「Final Stage of Charge Transfer Process in charge-Coupled Devices 」
  筆頭共著 IEEE Transaction on Electron Devices, vol ed-21,no4,
  pp.266-272, April 1974

(7) 「128 Bit Comparator」共著 IEEE Journal of Solid State Circuits,
Volume 11, No.5, pp.692-695, November 1976

P1976_128_bit_Comparator.pdf



When Hagiwara was an undergraduate student at Caltech in 1969,
Intel was still a very small venture company producing DRAM chips.





Hagiwara studied the MOS transistor techology and the scaling rules.

Hagiwara studied the physics of Bipolar and MOS transistor actions.







(8) 「市松模様蛇行CCDカラ ーカメラ」共著 昭和52年2月
TV学会方式回路研究 会論文誌 SO417B TBS36-3,
pp.1-18, February 1977

(9) 「高密度構造インターラ イン転送方式 CCD撮像 素子」共著 昭和53年4月
電子情報通信学会論文 SSD78-15 S0532B
Vol 78, No.15, pp.31-40, April 1978

(10) 「 Two Phase CCD with Narrow Channel Transfer Regions 」単著
   Japanese Journal of Applied Physics, Volume 17 Sup17-1, 1978,
   pp.255-261, November 1978

(11) 「ADVANCES in CCD IMAGERS 」単著  Technical Digest of IEEE
International Conference of CCD Image Sensors ( IEEE CCD'79
Conference ), Edinburgh, Scotland UK, September 1979

(12) 「A 380H X 488V CCD Imager with Narrow Channel Transfer Gates 」
筆頭共著 Japanese Journal of Applied Physics, Volume 18
   Sup 18-1, pp.335-340 November 1979

(13) 「インターライン転送方 式CCD撮像素子 」共著 
   テレビジョン学会論 文誌 ED481 S0209A (0386-4227)
   Vol3 No.33 , pp.47-52, January 1980

(14) 「2/3インチ 狭チャン ネル CCD撮像素子 : Single Chip Color Camera
 Using Narrow Channel CCD Imager with Overflow Drain」共著
   テレビジョン学会 方式回路電子装置 技術論文誌 TEBS 76-6,
   ED 611, pp.31-36, February 1981

(15) 「An Interline Transfer CCD Imager with High Density Structure 」
   共著 Technical Report Japan SSDM Conference, Tokyo May 1983,
    応 用 物 理 学 会 誌 Volume SSD 78-5, pp.47-52, May 1983

(16) 「ダイナミックビット 線負荷回路を用いた 25 nanosec 4MBit
    CMOS SRAM 」共著  電子情報通信学会論文誌 SDM89-13
    ICD 89-20 S0532B Vol 89 NO.66 (SDM89 9-18) , pp.25-30, June 1989

(17) 「 A 25-ns 4-Mbit CMOS SRAM with Dynamic Bit-Line Loads 」
    共著  IEEE Journal of Solid State Circuits, Volume 24, No.5,
    pp.1213-1218, October 1989

(18) 「DRAM/SRAM Technology and Problems」単著 
    Proceeding of the Institute of Electro Statics Japan,
    Volume 22, 6(1998), SSN 0386-2550, pp.277-281, July 1998

(19) 「High Density and High Quality Frame Transfer CCD Imager with Very
   Low Smear, Low dark Current and Very High Blue Sensitivity」単著
    IEEE Transaction on Electron Devices, Vol 43, no12,
    pp.2122-2130, December 1996

(20) 「Micro-Electronics for Home Entertainment」単著 Technical Digest
   of IEEE ESSCIRC International Conference ( ESSCIRC2001),
   Villach, Austria, September, 2001

*******************************
     群馬大学 客員教授時代 (2005~2007) の講義 リスト
*******************************
   
 Gunma_Univ_Lecture_Series_2005_to_2007_by_Hagiwara.pdf

https://kobaweb.ei.st.gunma-u.ac.jp/news/pdf/2017/2017-9-5hagiwara.pdf

https://kobaweb.ei.st.gunma-u.ac.jp/news/pdf/2017/Dr_hagiwara.pdf

https://kobaweb.ei.st.gunma-u.ac.jp/warehouse/nikkei-2007-2-6.pdf

*******************************

(21) 「SOI Design in Cell Processor and Beyond」単著 Technical Digest
   of IEEE ESSCIRC International Conference ( ESSCIRC2008),
   Edinburgh, Scotland UK, September 2008

https://ieeexplore.ieee.org/document/4681786

Invited Talk at ESSCIRC2008

(22) 「The p-n-p-n Diode in Future Linear Motor Cars and in Modern Images」
    単著 IEEE Solid-State Circuit Magazine, Summer issue pp. 6-8,
Special Issue on IEEE ISSCC2013 Invited Plenary Panel Talk, February 2013

(23) Japanese Patent 2014-135497

(24) 「離散フーリエ変換回路の設計」共著 電気学会集積回路研究
    Digest of Technical Papers, Izumo, Japan, July 2014

(25) 「非均等な時間間隔サンプリングされたデータの周波数成分ベクトルを求める演算回路
   共著 電子情報通信学会集積回路 (ICD) 研究会 
   Digest of Technical Papers ECT-14-060 , Kumamoto, Japan, August 2015



(26) 「Multichip CMOS Image Sensor Structure for Flash Image Acquisition 」単著
   IEEE International 3D Systems Integration Conference 2019 (3DIC2019)
   Digest of Technical Papers, Sendai, Japan, Paper4017, October 2019



(27) EDTM2020_PaperID3C-4

"Simulation and Device Characterization of the P+PN+P Junction Type
Pinned Photodiode and Schottky Barrier Photodiode"







*********************************************************







*********************************************************
What is Pinned Photodiode ?

Study Special Relativity Theory

What is Abura Wake Zan ?

Study Korean for Your Enjoyment

Enjoy C-programming.

IEEE_EDS_Kansai_Chapter_IMFEDK2006_Hagiwara.pdf

DRAM_SRAM_Technology_and_Problems_1998_07_29_Hagiwara

Pinned_Photodiode_must_have_a_heavy_doped_Channel_Stops



++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Pinned Photodiode must have the heavily doped channel stops nearby
and also completely buried signal charge collection and storage N region.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

In 1975, Sony proposed the Pinned surface PNP and PNPN junction type
dynamic phototransistor with the in pixel vertical overflow drain (VOD)
function for light detecting devices.

In 1978, Sony introduced one chip FT CCD image sensor with the Pinned
surface PNP junction type dynamic phototransistor which then became
the primary photodetector for CCD image sensors.

In 1984 Kodak called the Sony original Pinned surface PNP junction type
dynamic phototransistor simply as Pinnned Photodiode.

In 1987, Sony introduced a 2/3 inch, 380,000-pixel CCD image sensor
(ICX022) with the Pinned surface NPNP junction type dynamic Photo
Thryristor with VOD function which Sony then called simply as Hole
Accumulation Diode (HAD).

In the 1990s, the era of passport size video cameras demands compact
CCD image sensors with large numbers of pixels (1/2 inch or smaller
with 400,000 pixels or more).

In 1995, Kodak adopted Pinned Photodiode for CMOS image sensors.

Pinned Photodiodes, since invention by Sony in 1975, are still
the primary photodetector for CCD and CMOS image sensors now.

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++




*********************************************************

http://www.aiplab.com/index1_List_of_Books_and_Journal_Publication.html

http://www.aiplab.com/index2_Conference_Publication.html

http://www.aiplab.com/index3_International_Contributions_and_Awards.html

http://www.aiplab.com/index4_Important_Japanese_Patents.html

http://www.aiplab.com/index5_My_Work_Summary.html


http://www.aiplab.com/index6_Important_Publication_and_Patent_Works.html

*********************************************************


*********************************************************

hagiwara-yoshiaki@aiplab.com ( http://www.aiplab.com/ )

hagiwara@ssis.or.jp ( http://www.ssis.or.jp/en/index.html )

*********************************************************
           return to the TOP Page
*********************************************************